Linaro Connect MAD24 brought several meetings and discussions. We had
session where I presented what was done on SBSA Reference Platform
during last year and what are plans.
https://resources.linaro.org/en/resource/fnNt6vFpdT73EDhLZCxK6w has
video (with AI generated subtitles) and slides.
Current patch queue:
QEMU:
- move sbsa-ref to Neoverse-N2 by default
- switch from OpenBSD to FreeBSD in QEMU CI (for non-Linux coverage)
- update firmware used in QEMU CI to TF-A 2.11.0 + EDK2 stable202405
EDK2:
- multiple PCIe buses in NUMA setup
- update TF-A in edk2-non-osi to 2.11.0 like above
Some of my notes and ideas from Connect below.
1. Simple topology stuff.
Maybe instead of exporting whole /cpus/cpu-map/ we should export simple
topology:
cpus {
topology {
threads = <0x01>;
cores = <0x04>;
clusters = <0x01>;
sockets = <0x01>;
};
It gives everything we need. And much easier parsing in TF-A.
Had some thinking about exporting amount of cores per cluster (8 now,
virt uses 16 which is architecture maximum now) in case we would use it
in generation of PPTT in EDK2.
2. L1/L2 cache info per core in PPTT.
I was asked can we put L1/L2 cache information for each core in PPTT. We
would need to change that code while handling topology stuff so why not
do that at same time. It would be used once we get MPAM support.
3. Move to Neoverse-N2 by default.
N2 is v9.0 cpu which gives us several features like RME, RNG, SVE etc
enabled by default. There is a work related with CCA (Confidential
Computing) which requires RME. Presence of RNG allows us to provide
EFI_PROTOCOL_RNG to kernel.
4. EDK2 needs changes for SMCCC 1.5
ArmCallSmc*() functions make use of x0-x7 registers (x0-x7 as arguments,
x0-x3 as results) like it was designed in 2016 in "SMC Calling
Conventions" specification. But those calls can use x0-x17 (both as
arguments and results) since 2020 and our topology stuff needs that.
https://developer.arm.com/documentation/den0028/latest/
As part of it should also use ArmCallSmc() instead of ArmCallSmc[0-3]()
functions - this way we can use more arguments/results without a need
for creation of all ArmCallSmc[0-17]() calls.
5. Firmware Handoff protocol
FH protocol is very simple protocol to share data between firmware
layers. We could use it instead of Devicetree so people would stop
suggesting 'add this or that to DT'.
https://github.com/FirmwareHandoff/firmware_handoff
We should do it sooner than later - 'adapt spec now, or adapt to spec
later' kind.
6. CPU hotplug
So far the only data is 'check with cpu hotplug, -smp and maxcpus stuff'
but it may be interesting to know do we (can) have it or not.
Any opinions? Something to add, comments?
There is a patch for changing MPIDR_EL1 handling on qemu-devel ML [1]
which (if merged) will force us to do changes to SBSA-ref in QEMU, TF-A
and probably EDK2 too.
1.
https://lore.kernel.org/qemu-devel/20240419183135.12276-1-dorjoychy111@gmai…
Details:
MPIDR_EL1 register keeps cpu topology information. There are 2 or 4 8bit
fields called Aff0-Aff3.
For now Aff0 and Aff1 are used in QEMU:
Aff0 - keeps core number (8 cores per cluster)
Aff1 - keeps cluster number
The plan is to use 0/1 for cores below Neoverse-N1 and 0-3 on higher
ones with Aff0 being 0 as it is used for threads which are forbidden in
designed emulated by QEMU.
So whole topology can be stored:
Aff0 - thread
Aff1 - core
Aff2 - cluster
Aff3 - socket
What it means for us?
First of all: platform version MAJOR bump. So we would have
platform_version = 1.0 as virtual hardware changes force firmware changes.
Second: TF-A freeze is coming. Would be good to not have to wait for
November and 2.12 release.
We need to drop sbsa_topology.c from TF-A as it assumes Aff0/1 way and
errors out on Aff0-3 way.
Generation of PPTT in EDK2 needs to be changed too. Good side is that we
may drop DT/SMC way and read socket/cluster/core/thread from MPIDR_EL1
directly.
To make things easier I would like to drop support for Cortex-A57/A72
from sbsa-ref. They have Aff0/1 only and would require special handling
in firmware. We would need it anyway as people tend to use misc versions
of QEMU but this way code will get less and less used. And v8.2 will be
minimal version.
Opinions?
BSA ACS run on SBSA Reference platform gives 8 skipped tests:
303 : Check SMMU Large Physical Addr Support
403 : Memory mapped timer check
404 : Generate Mem Mapped SYS Timer Intr
405 : Restore PE timer on PE wake up
505 : Wake from System Timer Int
606 : 16550 compatible UART
806 : Legacy int must be SPI & lvl-sensitive
817 : Check Direct Transl P2P Support
303 wants SMMU with LPA support but skips when cpu lacks it.
606 checks for 16550 UART, we have PL011 one (you need one of them)
403, 404, 405, 505 require memory mapped system timers which we do not
have. But we have PE timer always on (test 402) so can ignore them.
806 is platform specific and needs to be populated by partners with
system legacy irq map.
817 wants RP type device with P2P and ATS support. Skips if not present.
To support the removal of the DT in EDK2, we can parse the memory related information in TF-A and pass them to EDK2 through SMC.
Xiong Yining (1):
feat(qemu_sbsa): report the information of memory via SMC
plat/qemu/qemu_sbsa/sbsa_sip_svc.c | 84 +++++++++++++++++++++++++++++-
1 file changed, 83 insertions(+), 1 deletion(-)
--
2.34.1
Enable CPU cluster support on SbsaQemu platform, so that users can
specify a 4-level CPU hierarchy sockets/clusters/cores/threads. And this
topology can be passed to the firmware through DT cpu-map.
xiongyining1480 (2):
hw/arm/sbsa-ref:Enable CPU cluster on ARM sbsa machine
hw/arm/sbsa-ref: Add cpu-map to device tree
hw/arm/sbsa-ref.c | 36 ++++++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
--
2.34.1
When SaSbQemu platform is configured with multi memory nodes, like
numa architecture, os will ignore any memory node in the device tree
except the first one.The kernel reads UEFI memory map for memory
information when booting via UEFI.However UEFI only allocates the
first memory node memory space for SbsaQemu platform, in this
scenario we can use the GCD services to add memory spaces
for high memory node.
Changes in v2:
- get the information of memory via SMC rather than FdtClientDxe.
- add a new driver rather than use HighMemDxe.
Xiong Yining (1):
SbsaQemu: add memory space for the high memory nodes
Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 3 +-
Platform/Qemu/SbsaQemu/SbsaQemu.fdf | 1 +
.../SbsaQemuHighMemDxe/SbsaQemuHighMemDxe.inf | 43 ++++++
.../SbsaQemuHighMemDxe/SbsaQemuHighMemDxe.c | 133 ++++++++++++++++++
4 files changed, 179 insertions(+), 1 deletion(-)
create mode 100644 Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuHighMemDxe/SbsaQemuHighMemDxe.inf
create mode 100644 Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuHighMemDxe/SbsaQemuHighMemDxe.c
--
2.34.1
