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[PATCH] [Morello] CHERI-style compact printing format

by Luis Machado

This patch adds CHERI-style compact printing format to GDB and uses it by default. gdbsupport/ChangeLog: YYYY-MM-DD Luis Machado <luis.machado(a)arm.com> * capability.cc (cap_short_perms_strings): Remove. (capability::is_null_derived): New member function. (capability::to_str): Document and handle new CHERY-style printing format. * capability.h (cap_constants): Document the CAP_SEAL_TYPE_* constants. (struct capability) <is_null_derived>: New member function prototype. --- gdbsupport/capability.cc | 118 ++++++++++++++++++++++++++------------- gdbsupport/capability.h | 8 +++ 2 files changed, 88 insertions(+), 38 deletions(-) diff --git a/gdbsupport/capability.cc b/gdbsupport/capability.cc index 6551bab678..5ced9b6762 100644 --- a/gdbsupport/capability.cc +++ b/gdbsupport/capability.cc @@ -76,31 +76,6 @@ static const char *cap_perms_strings[] = "Load" }; -/* Short version of permission string names, indexed by bit number from - permissions - Valid bits are 0 through 17. */ -static const char *cap_short_perms_strings[] = -{ - "G", - "E", - "U0", - "U1", - "U2", - "U3", - "MLd", - "CID", - "BrUn", - "Sys", - "Un", - "Sl", - "StLoC", - "StC", - "LdC", - "X", - "St", - "Ld" -}; - /* Returns a capability, derived from the input capability, with base address set to the value of the input capability and the length set to a given value. If precise bounds setting is not possible, either the bounds are @@ -548,6 +523,14 @@ capability::set_offset (uint64_t offset) set_value (get_base () + offset); } +/* Returns true if the capability has the top 64 bits equal to zero. + Returns false otherwise. */ + +bool capability::is_null_derived (void) +{ + return _bits (m_cap, 127, 64) == 0; +} + /* Returns a string representation of the capability. If COMPACT is true, use a less verbose form. Otherwise print @@ -556,20 +539,79 @@ capability::set_offset (uint64_t offset) std::string capability::to_str (bool compact) { - /* The printing format is the following: - {tag = %d, address = 0x%016x, permissions = {[%s], otype = 0x%04x, - [range = [0x%016x - 0x%016x)}} + /* There are 3 printing formats. + + - (1) - If the top 64 bits are 0 and the tag is false, then we should print + the capability's value as a pointer. Example: 0xdeadbeef. + + - (2) - If the top 64 bits are non-zero and the representation is + COMPACT, the capability has the following format: + + - (3) - If the top 64 bits are non-zero and the representation is not + COMPACT, the capability has the following format: + + {tag = %d, address = 0x%016x, permissions = {[%s], otype = 0x%04x, + [range = [0x%016x - 0x%016x)}} */ - std::string cap_str (""); - std::string tag_str (get_tag ()? "1" : "0"); + std::string val_str (""); - std::string perm_str (""); - std::string otype_str (""); - std::string range_str (""); /* Capability value. */ val_str += core_addr_to_string_nz (get_value ()); + /* Format 1. */ + if (is_null_derived ()) + return val_str; + + std::string cap_str (""); + std::string perm_str (""); + std::string range_str (""); + + /* Format 2. */ + if (compact) + { + /* Handle compact permissions output. */ + if (check_permissions (1 << cap_perms_load)) + perm_str += "r"; + if (check_permissions (1 << cap_perms_store)) + perm_str += "w"; + if (check_permissions (1 << cap_perms_execute)) + perm_str += "x"; + if (check_permissions (1 << cap_perms_load_cap)) + perm_str += "R"; + if (check_permissions (1 << cap_perms_store_cap)) + perm_str += "W"; + if (check_permissions (1 << cap_perms_executive)) + perm_str += "E"; + + /* Handle capability range. */ + range_str += core_addr_to_string_nz (get_base ()); + range_str += "-"; + range_str += core_addr_to_string_nz (get_limit ()); + + std::string attr_str (""); + + /* Handle attributes. */ + if (get_tag () == false) + attr_str = "invalid "; + if (get_otype () == CAP_SEAL_TYPE_RB) + attr_str = "sentry "; + if (is_sealed ()) + attr_str = "sealed "; + + cap_str += "{"; + cap_str = val_str + " [" + perm_str + "," + range_str + "]"; + + if (!attr_str.empty ()) + cap_str += " ( " + attr_str + ")"; + + cap_str += "}"; + + return cap_str; + } + + /* Format 3. */ + /* Permissions. */ perm_str += "["; @@ -577,15 +619,13 @@ capability::to_str (bool compact) if (check_permissions (1 << i)) { perm_str += " "; - - if (compact) - perm_str += cap_short_perms_strings[i]; - else - perm_str += cap_perms_strings[i]; + perm_str += cap_perms_strings[i]; } perm_str += " ]"; + std::string otype_str (""); + /* Object type, if sealed. */ otype_str += core_addr_to_string_nz (get_otype ()); @@ -596,6 +636,8 @@ capability::to_str (bool compact) range_str += core_addr_to_string_nz (get_limit ()); range_str += ")"; + std::string tag_str (get_tag ()? "1" : "0"); + /* Assemble the capability string. */ cap_str += "{tag = " + tag_str + ", address = " + val_str + ", " + "permissions = {" + perm_str + " "; diff --git a/gdbsupport/capability.h b/gdbsupport/capability.h index fd94768e43..d77d8094a1 100644 --- a/gdbsupport/capability.h +++ b/gdbsupport/capability.h @@ -250,8 +250,11 @@ enum cap_constants { CAP_PERM_LOAD = (1<<17), CAP_PERM_LOAD_BIT = CAP_PERMS_LO_BIT+17, + /* Equivalent to CHERI's OTYPE_RESERVED3. */ CAP_SEAL_TYPE_LB = 3, + /* Equivalent to CHERI's OTYPE_RESERVED2. */ CAP_SEAL_TYPE_LPB = 2, + /* Equivalent to CHERI's OTYPE_SENTRY. */ CAP_SEAL_TYPE_RB = 1, CAP_TAG_BIT = 128, @@ -542,6 +545,11 @@ struct capability { otherwise. */ bool is_equal (void) const; + /* Returns true if the capability has the top 64 bits equal to zero. + Returns false otherwise. */ + + bool is_null_derived (void); + /* Printing functions. */ /* Returns a string representation of the capability. -- 2.25.1

3 years, 9 months

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Re: [Gnu-morello] [PATCH 4/9] Support data_capability and code_capability types + update target description

by J.R.T. Clarke

Hi Luis, On 11 Nov 2020, at 18:45, Luis Machado via Gnu-morello <gnu-morello(a)op-lists.linaro.org> wrote: > > From: Luis Machado <luis.machado(a)arm.com> > > Support the data_capability and code_capability types, which the capability > counterparts of the data_ptr and code_ptr types. > > Adjust the Morello C registers to be of data_capability and code_capability > types. Out of interest, what's the justification behind this? In general the C registers could be either data or code capabilities depending on whether they're storing a function pointer (at least without a descriptor-based ABI). Surveying the AArch64 and RISC-V XML files I see that data_ptr and code_ptr are only used in cases where the registers are definitely only used for that, i.e. PC is code_ptr and SP is data_ptr on AArch64, and on RISC-V RA also gets code_ptr and GP, TP and FP get data_ptr, with everything else being left as an integer. Should the CHERI equivalents not mirror that, with the general-purpose registers remaining (u)intcap and only PCC and CSP having more-specific types? Jess

3 years, 10 months

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[PATCH 1/9] Guard places using Morello C registers

by Luis Machado

From: Luis Machado <luis.machado(a)arm.com> Make sure we only use the C registers if they have been detected. gdb/ChangeLog: YYYY-MM-DD Luis Machado <luis.machado(a)arm.com> * aarch64-tdep.c (aarch64_prologue_prev_register): Guard use of C registers. (aarch64_dwarf2_prev_register): Likewise. (aarch64_dwarf2_frame_init_reg): Likewise. * aarch64-linux-nat.c (aarch64_linux_nat_target::store_registers): Likewise. --- gdb/aarch64-linux-nat.c | 6 +++++- gdb/aarch64-tdep.c | 23 ++++++++++++++++++----- 2 files changed, 23 insertions(+), 6 deletions(-) diff --git a/gdb/aarch64-linux-nat.c b/gdb/aarch64-linux-nat.c index 7e1763e8ea..dc006de7f0 100644 --- a/gdb/aarch64-linux-nat.c +++ b/gdb/aarch64-linux-nat.c @@ -582,7 +582,11 @@ aarch64_linux_nat_target::store_registers (struct regcache *regcache, else if (regno < AARCH64_V0_REGNUM) { store_gregs_to_thread (regcache); - fetch_cregs_from_thread (regcache); + + /* If we have capability registers, refresh them when we store to + the general register set. */ + if (tdep->has_capability ()) + fetch_cregs_from_thread (regcache); } else if (tdep->has_sve ()) store_sveregs_to_thread (regcache); diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c index cb6f468363..16c85e3946 100644 --- a/gdb/aarch64-tdep.c +++ b/gdb/aarch64-tdep.c @@ -1401,7 +1401,10 @@ aarch64_prologue_prev_register (struct frame_info *this_frame, = aarch64_make_prologue_cache (this_frame, this_cache); struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); - int pcc_regnum = tdep->cap_reg_base + 31; + + int pcc_regnum = -1; + if (tdep->has_capability ()) + pcc_regnum = tdep->cap_reg_base + 31; /* If we are asked to unwind the PC, then we need to return the LR instead. The prologue may save PC, but it will point into this @@ -1465,7 +1468,9 @@ aarch64_prologue_prev_register (struct frame_info *this_frame, | | | |<- SP +----------+ */ - int csp_regnum = tdep->cap_reg_base + 32; + int csp_regnum = -1; + if (tdep->has_capability ()) + csp_regnum = tdep->cap_reg_base + 32; if (prev_regnum == AARCH64_SP_REGNUM || prev_regnum == csp_regnum) return frame_unwind_got_constant (this_frame, prev_regnum, @@ -1611,7 +1616,9 @@ aarch64_dwarf2_prev_register (struct frame_info *this_frame, struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); CORE_ADDR lr; - int pcc_regnum = tdep->cap_reg_base + 31; + int pcc_regnum = -1; + if (tdep->has_capability ()) + pcc_regnum = tdep->cap_reg_base + 31; if (regnum == AARCH64_PC_REGNUM || regnum == pcc_regnum) { @@ -1635,8 +1642,14 @@ aarch64_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, struct frame_info *this_frame) { struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); - int pcc_regnum = tdep->cap_reg_base + 31; - int csp_regnum = tdep->cap_reg_base + 32; + int pcc_regnum = -1; + int csp_regnum = -1; + + if (tdep->has_capability ()) + { + pcc_regnum = tdep->cap_reg_base + 31; + csp_regnum = tdep->cap_reg_base + 32; + } if (regnum == AARCH64_PC_REGNUM || regnum == pcc_regnum) { -- 2.25.1

3 years, 10 months

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[CHERI/AArch64] Announcing the Morello branch in binutils-gdb

by Kyrylo Tkachov

Hi all, We have pushed the users/ARM/morello-binutils-gdb-master branch to the binutils repo implementing initial support for the Morello architecture [1]. The Morello architecture is a prototype implementation of the capability-based CHERI [2] architecture in AArch64, intended to promote research into capability architectures and their deployment. The work builds on multiple years of research and development by the Cambridge University Computer Laboratory of the CHERI project and we are very excited to explore its application to the Arm architecture. I encourage you to explore the CHERI specifications [2] and the software already available. The gas, objdump and ld components on the branch are in reasonable shape and have been used to assemble and link a Linux kernel with Morello modifications. The GDB port is more of a work in progress. We have published an LLVM-derived Morello toolchain [3], based on the CHERI toolchain, that can be used to try out the compiler support available for Morello. The ABI specifications (available on developer.arm.com [4]) are in an alpha state and are likely to change going forward. There are also related publications on the programming model [5] and language runtime semantics [6] from the CHERI project. There is work ongoing on porting GCC and glibc to Morello and we will share more details as that work progresses. As Morello is a prototype architecture we intend to maintain the toolchain components on a branch rather than integrate it into master. We are interested in any feedback you have on the code. To report bugs please use the GitLab mirror set up at: https://git.morello-project.org/morello-gnu-toolchain/binutils-gdb Please send any patches or start discussions on the gnu-morello [7] list, kindly hosted by Linaro. Maintainers for the branch are: * GDB: Luis Machado <luis.machado(a)linaro.org> * Binutils: Matthew Malcomson <matthew.malcomson(a)arm.com> * Binutils: Kyrylo Tkachov <kyrylo.tkachov(a)arm.com> We are very excited to investigate the challenges and possibilities of a capability-based architecture. Please have a read through the links below if this project is of interest to you and reach out to us on the list [7] If you have any feedback or discussions about the Morello architecture and program you are welcome to reach out on the forums [8]. We look forward to sharing more in the near future. Last but not least, I'd like to say a big thank you to Siddhesh Poyarekar for the binutils port described here. Thanks, Kyrill [1] https://developer.arm.com/architectures/cpu-architecture/a-profile/morello [2] https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/ [3] https://git.morello-project.org/morello/llvm-project [4] https://developer.arm.com/architectures/system-architectures/software-stand… [5] https://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-947.pdf [6] https://www.cl.cam.ac.uk/research/security/ctsrd/pdfs/201904-asplos-cheriab… [7] https://op-lists.linaro.org/mailman/listinfo/gnu-morello [8] https://community.arm.com/developer/research/morello/

3 years, 10 months

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Re: [Gnu-morello] FW: [binutils-gdb] Add README-morello file to binutils repo

by Luis Machado

Seems to work! On 10/29/20 10:40 AM, Kyrylo Tkachov via Gnu-morello wrote: > Resending to test attachment archival. > >> -----Original Message----- >> From: Kyrylo Tkachov >> Sent: 29 October 2020 11:23 >> To: gnu-morello(a)op-lists.linaro.org >> Cc: nd <nd(a)arm.com> >> Subject: [binutils-gdb] Add README-morello file to binutils repo >> >> Hi all, >> >> This patch adds a README-morello file that describes the >> users/ARM/morello-binutils-gdb-master branch, its maintainers and points >> to this list. >> >> Pushed to the sourceware repo on the users/ARM/morello-binutils-gdb- >> master branch. >> >> Thanks, >> Kyrill > IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. > >

3 years, 10 months

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[binutils-gdb] Add README-morello file to binutils repo

by Kyrylo Tkachov

Hi all, This patch adds a README-morello file that describes the users/ARM/morello-binutils-gdb-master branch, its maintainers and points to this list. Pushed to the sourceware repo on the users/ARM/morello-binutils-gdb-master branch. Thanks, Kyrill

3 years, 10 months

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[AArch64] Announcing the Morello branch in binutils-gdb

by Kyrylo Tkachov

Hi all, We, Arm, have pushed the users/ARM/morello-binutils-gdb-master branch to the binutils repo implementing initial support for the Morello architecture [1]. The Morello architecture is a prototype implementation of the capability-based CHERI [2] architecture in AArch64, intended to promote research into capability architectures and their deployment. The gas, objdump and ld components on the branch are in reasonable shape and have been used to assemble and link a Linux kernel with Morello modifications. The GDB port is more of a work in progress. All code is liable to change going forward, as our understanding of the deployment opportunities and challenges evolves. We have published an LLVM-based Morello toolchain [3] that can be used to try out the compiler support available for Morello. The ABI specifications (available on developer.arm.com [4]) are in an alpha state and are likely to change going forward. There is work ongoing on porting GCC and glibc to Morello and we will share more details as that work progresses. As Morello is a prototype architecture we intend to maintain the toolchain components on a branch rather than integrate it into master. We are interested in any feedback you have on the code. To report bugs please use the GitLab mirror set up at: https://git.morello-project.org/morello-gnu-toolchain/binutils-gdb Please send any patches or start discussions on the gnu-morello [5] list, kindly hosted by Linaro. Maintainers for the branch are: * GDB: Luis Machado <luis.machado(a)linaro.org> * Binutils: Matthew Malcomson <matthew.malcomson(a)arm.com> * Binutils: Kyrylo Tkachov <kyrylo.tkachov(a)arm.com> We are very excited to investigate the challenges and possibilities of a capability-based architecture. Please have a read through the links below if this project is of interest to you and reach out to us on the list [5] If you have any feedback or discussions about the Morello architecture and program you are welcome to reach out on the forums [6]. We look forward to sharing more in the near future. Last but not least, I'd like to say a big thank you to Siddhesh Poyarekar for the binutils port described here. Thanks, Kyrill [1] https://developer.arm.com/architectures/cpu-architecture/a-profile/morello [2] https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/ [3] https://git.morello-project.org/morello/llvm-project [4] https://developer.arm.com/architectures/system-architectures/software-stand… [5] https://op-lists.linaro.org/mailman/listinfo/gnu-morello [6] https://community.arm.com/developer/research/morello/

3 years, 10 months

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