When we started to account for function stubs when determining our PCC bounds and section bounds we stopped including padding to make PCC bounds precise in the highest section that should be included in the PCC range. Instead we put such padding *after* that section.
Our patch handling IFUNC's was written in parallel, and its testcases were using the previous setup (where PCC padding was included in the last section). Hence when calculating a fragment that we should see in our testcase we took the highest address in the last RELRO section.
After the application of both patches that approach no longer works. With the new mechanism for padding there is no longer in general a guarantee that any value in the section table could correspond to the PCC bounds (since the alignment of the first writeable section could be high enough such that the PCC bounds are somewhere between the end of the last RELRO section and the start of the first WRITE section). However for all these testcases the start of the first WRITE section seems good enough to not be flaky.
############### Attachment also inlined for ease of reply ###############
diff --git a/ld/testsuite/ld-aarch64/morello-ifunc-a.d b/ld/testsuite/ld-aarch64/morello-ifunc-a.d index f36b0945cb554a841fa16dd58f96d7bec7da29ee..a9c3b65073dbd6dcd2c2af60e1bfca43957febb4 100644 --- a/ld/testsuite/ld-aarch64/morello-ifunc-a.d +++ b/ld/testsuite/ld-aarch64/morello-ifunc-a.d @@ -14,10 +14,11 @@ Idx Name Size VMA LMA File off Algn #record: PCC_START 0 .[^ ]* +[0-9a-f]* ([0-9a-f]+) .* CONTENTS, ALLOC, LOAD, READONLY, DATA -#record: PCC_LAST_SIZE PCC_LAST_START #... - *[0-9]+ .got.plt *([0-9a-f]+) ([0-9a-f]+) .* + *[0-9]+ .got.plt *[0-9a-f]+ [0-9a-f]+ .* CONTENTS, ALLOC, LOAD, DATA +#record: PCC_END + *[0-9]+ .[^ ]* +[0-9a-f]* ([0-9a-f]+) .* #... Disassembly of section .plt:
@@ -78,7 +79,7 @@ Disassembly of section .got:
#check: PLT_ADDEND format %x [expr "0x$PLTADDR - 0x$PCC_START + 1"] #check: FRAGBASE format %08x 0x$PCC_START -#check: FRAGSIZE format %08x [expr "0x$PCC_LAST_SIZE + 0x$PCC_LAST_START - 0x$PCC_START"] +#check: FRAGSIZE format %08x [expr "0x$PCC_END - 0x$PCC_START"] #check: FRAGMENT_LOC aarch64_page_plus_decimal_offset $GOT_PAGE $FOO_GOTOFF_DECIMAL #... *FRAGMENT_LOC: FRAGBASE .* @@ -98,7 +99,6 @@ Disassembly of section .got.plt: *[0-9a-f]+: 00000000 .* *[0-9a-f]+: FRAGSIZE .* *[0-9a-f]+: 04000000 .* - ...
Disassembly of section .data:
diff --git a/ld/testsuite/ld-aarch64/morello-ifunc.d b/ld/testsuite/ld-aarch64/morello-ifunc.d index 11ad08d9a2f3c87fc23bb7ba9b3f7ffad07c006a..3a95f3d259ac0cd83df2ea4021f660b059e9dbd9 100644 --- a/ld/testsuite/ld-aarch64/morello-ifunc.d +++ b/ld/testsuite/ld-aarch64/morello-ifunc.d @@ -19,10 +19,11 @@ Idx Name Size VMA LMA File off Algn #record: PCC_START 0 .[^ \t]* +[0-9a-f]* ([0-9a-f]+) .* CONTENTS, ALLOC, LOAD, READONLY, DATA -#record: LAST_PCC_SEC_SIZE LAST_PCC_SEC_START #... - *[0-9]+ .got.plt *([0-9a-f]+) ([0-9a-f]+) .* + *[0-9]+ .got.plt *[0-9a-f]+ [0-9a-f]+ .* CONTENTS, ALLOC, LOAD, DATA +#record: PCC_END + *[0-9]+ .[^ ]* +[0-9a-f]* ([0-9a-f]+) .* #... SYMBOL TABLE: #record: RELA_DYN_END @@ -118,7 +119,7 @@ Disassembly of section .got:
#clearcheck: #check: FRAGMENT_BASE aarch64_8digit_addr $PCC_START -#check: FRAGMENT_SIZE format %08x [expr "0x$LAST_PCC_SEC_START + 0x$LAST_PCC_SEC_SIZE - 0x$PCC_START"] +#check: FRAGMENT_SIZE format %08x [expr "0x$PCC_END - 0x$PCC_START"] #check: FRAGMENT_LOC format %x 0x$FOO_GOT #... *FRAGMENT_LOC: FRAGMENT_BASE .* diff --git a/ld/testsuite/ld-aarch64/morello-ifunc1-a.d b/ld/testsuite/ld-aarch64/morello-ifunc1-a.d index 062973bab00df7824f756e8f4ccdf1f051c6e23b..7a53551ac1c783279140a0c56e9fe53f4d8202db 100644 --- a/ld/testsuite/ld-aarch64/morello-ifunc1-a.d +++ b/ld/testsuite/ld-aarch64/morello-ifunc1-a.d @@ -21,10 +21,11 @@ Idx Name Size VMA LMA File off Algn #record: PCC_START 0 .[^ ]+ +[0-9a-f]+ ([0-9a-f]+) [0-9a-f]+ [0-9a-f]+ 2**. CONTENTS, ALLOC, LOAD, READONLY, DATA -#record: PCC_LAST_SIZE PCC_LAST_START #... - *[0-9]+ .got.plt +([0-9a-f]+) ([0-9a-f]+) [0-9a-f]+ [0-9a-f]+ 2**. + *[0-9]+ .got.plt *[0-9a-f]+ [0-9a-f]+ .* CONTENTS, ALLOC, LOAD, DATA +#record: PCC_END + *[0-9]+ .[^ ]* +[0-9a-f]* ([0-9a-f]+) .* #... Disassembly of section .plt:
@@ -79,7 +80,7 @@ Disassembly of section .got.plt:
#check: GOTLOC aarch64_page_plus_decimal_offset $PLTGOT_PAGE $PLTGOT_DEC_OFF #check: FRAGBASE format %08x 0x$PCC_START -#check: FRAGSIZE format %08x [expr "0x$PCC_LAST_SIZE + 0x$PCC_LAST_START - 0x$PCC_START"] +#check: FRAGSIZE format %08x [expr "0x$PCC_END - 0x$PCC_START"] #check: FOO_OFFSET format %x [expr "0x$FOO_ADDR + 1 - 0x$PCC_START"] [0-9a-f]+ <.*>: ... diff --git a/ld/testsuite/ld-aarch64/morello-ifunc1-b.d b/ld/testsuite/ld-aarch64/morello-ifunc1-b.d index 062973bab00df7824f756e8f4ccdf1f051c6e23b..7a53551ac1c783279140a0c56e9fe53f4d8202db 100644 --- a/ld/testsuite/ld-aarch64/morello-ifunc1-b.d +++ b/ld/testsuite/ld-aarch64/morello-ifunc1-b.d @@ -21,10 +21,11 @@ Idx Name Size VMA LMA File off Algn #record: PCC_START 0 .[^ ]+ +[0-9a-f]+ ([0-9a-f]+) [0-9a-f]+ [0-9a-f]+ 2**. CONTENTS, ALLOC, LOAD, READONLY, DATA -#record: PCC_LAST_SIZE PCC_LAST_START #... - *[0-9]+ .got.plt +([0-9a-f]+) ([0-9a-f]+) [0-9a-f]+ [0-9a-f]+ 2**. + *[0-9]+ .got.plt *[0-9a-f]+ [0-9a-f]+ .* CONTENTS, ALLOC, LOAD, DATA +#record: PCC_END + *[0-9]+ .[^ ]* +[0-9a-f]* ([0-9a-f]+) .* #... Disassembly of section .plt:
@@ -79,7 +80,7 @@ Disassembly of section .got.plt:
#check: GOTLOC aarch64_page_plus_decimal_offset $PLTGOT_PAGE $PLTGOT_DEC_OFF #check: FRAGBASE format %08x 0x$PCC_START -#check: FRAGSIZE format %08x [expr "0x$PCC_LAST_SIZE + 0x$PCC_LAST_START - 0x$PCC_START"] +#check: FRAGSIZE format %08x [expr "0x$PCC_END - 0x$PCC_START"] #check: FOO_OFFSET format %x [expr "0x$FOO_ADDR + 1 - 0x$PCC_START"] [0-9a-f]+ <.*>: ... diff --git a/ld/testsuite/ld-aarch64/morello-ifunc1.d b/ld/testsuite/ld-aarch64/morello-ifunc1.d index c205f15a3044c52d9124b3cd6e1114204f49b606..d7687dd22e622e14450ba539ac23d7bbbc06cfd0 100644 --- a/ld/testsuite/ld-aarch64/morello-ifunc1.d +++ b/ld/testsuite/ld-aarch64/morello-ifunc1.d @@ -20,10 +20,11 @@ Idx Name Size VMA LMA File off Algn #record: PCC_START 0 .[^ ]+ +[0-9a-f]+ ([0-9a-f]+) [0-9a-f]+ [0-9a-f]+ 2**. CONTENTS, ALLOC, LOAD, READONLY, DATA -#record: PCC_LAST_SIZE PCC_LAST_START #... - *[0-9]+ .got.plt +([0-9a-f]+) ([0-9a-f]+) [0-9a-f]+ [0-9a-f]+ 2**. + *[0-9]+ .got.plt *[0-9a-f]+ [0-9a-f]+ .* CONTENTS, ALLOC, LOAD, DATA +#record: PCC_END + *[0-9]+ .[^ ]* +[0-9a-f]* ([0-9a-f]+) .* #...
Disassembly of section .rela.plt: @@ -93,7 +94,7 @@ Disassembly of section .got.plt:
#check: GOTLOC format %x 0x$PLTGOT_LOC #check: FRAGBASE format %08x 0x$PCC_START -#check: FRAGSIZE format %08x [expr "0x$PCC_LAST_SIZE + 0x$PCC_LAST_START - 0x$PCC_START"] +#check: FRAGSIZE format %08x [expr "0x$PCC_END - 0x$PCC_START"] [0-9a-f]+ <.*>: ... *GOTLOC: FRAGBASE .* diff --git a/ld/testsuite/ld-aarch64/morello-ifunc4.d b/ld/testsuite/ld-aarch64/morello-ifunc4.d index ceb213b2114e4ae8e4d9388b2f69f500ce67d2aa..a44f5fde67645390bc1b834d4d9dab49e0e8fefd 100644 --- a/ld/testsuite/ld-aarch64/morello-ifunc4.d +++ b/ld/testsuite/ld-aarch64/morello-ifunc4.d @@ -13,10 +13,11 @@ Idx Name Size VMA LMA File off Algn #record: PCC_START 0 .[^ ]+ +[0-9a-f]+ ([0-9a-f]+) [0-9a-f]+ [0-9a-f]+ 2**. CONTENTS, ALLOC, LOAD, READONLY, DATA -#record: PCC_LAST_SIZE PCC_LAST_START #... - *[0-9]+ .got.plt +([0-9a-f]+) ([0-9a-f]+) [0-9a-f]+ [0-9a-f]+ 2**. + *[0-9]+ .got.plt *[0-9a-f]+ [0-9a-f]+ .* CONTENTS, ALLOC, LOAD, DATA +#record: PCC_END + *[0-9]+ .[^ ]* +[0-9a-f]* ([0-9a-f]+) .* #... SYMBOL TABLE: #record: RELA_IPLT_END @@ -140,7 +141,7 @@ Disassembly of section .got:
#check: GOTLOC format %x 0x$GOT_IFUNC_LOC #check: FRAGBASE format %08x 0x$PCC_START -#check: FRAGSIZE format %08x [expr "0x$PCC_LAST_SIZE + 0x$PCC_LAST_START - 0x$PCC_START"] +#check: FRAGSIZE format %08x [expr "0x$PCC_END - 0x$PCC_START"] [0-9a-f]+ <.*>: *[0-9a-f]+: 00000000 .* *[0-9a-f]+: 00000000 .*